"claiming Process Unveiled: How To Successfully Navigate Travel Insurance Claims In Australia" - Another year, another TechDay from Arm. For the past few years, Arm's event has been running like clockwork in the May time frame, revealing the latest flagship CPU and GPU IP each time. This year is no exception, as the event is back on the American side of the Atlantic in Austin, Texas, where Arm has one of its main design centers.
Two years ago during the Cortex A73 reveal, I talked a bit more about Arm's CPU design teams and how they are divided between locations and product lines. The main design centers for the Cortex-A series CPUs are located in Austin, Texas; Cambridge, United Kingdom and Sophia-Antipolis in the south of France near Nice. Over the past two years, the Cortex A73 and Cortex A75 were designs that came out mainly from the Sophia team, while the Cortex A53 and more recently the A55 were designs coming out of Cambridge. That said, we haven't seen any of the latest designs coming out of Austin, and the last of the "Austin family" CPUs were the A57 and A72.
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The project that was being worked on in Austin has been hyped for several years - I remember already when the A73 was released in 2016, the company moved some elements from the advanced future microarchitecture to the back-end pipeline, especially the FP. /side SIMD. The Cortex A75 was further noted to be pulling more features from this mysterious new project.
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Today we can finally reveal what the Austin team has been working on – and it's big. The new Cortex A76 is a completely new microarchitecture that was built from scratch and laid the foundation for at least two more generations of processors, which I'll call "the second generation of the Austin family."
The Cortex A76 is important for Arm in terms of design, as it represents a fresh start from a clean slate. It's rare that an IP claims to be able to do this, as it represents a large investment of resources and time, and if it wasn't for the Sophia design team that has taken the wheel over the last two product generations, it wouldn't make sense. to perform. In particular, the performance of the CPU design teams should be highlighted, as Arm claims that it is the 5
Product generation "annual beat", where the company delivers a new microarchitecture every new year. Think of it as an analog of Intel's past Tick-Tock strategy, but rather a Tock-Tock-Tock for Arm with a steady CAGR (compound annual growth rate) of 20-25% each generation coming from µarch improvements.
So what is Cortex A76? In Arm's words, it's a powerful "notebook-grade" processor with mobile efficiency. The vision of the A76 as a notebook-class processor was emphasized during the TechDay presentation, so it seems that Arm is really using the big IP performance boost to cater to new market segments like the emerging "Always Connected PCs" that Qualcomm is spearheading with its platforms SoC.
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The Cortex A76 microarchitecture has been designed with high performance while maintaining energy efficiency. Starting from a clean slate allowed designers to remove bottlenecks throughout the design and break through previous micro-architectural constraints. The focus was once again on maximum performance while maintaining the energy efficiency that is suitable for smartphones.
In broad metrics, we promise the following in actual products using the A76: 35% performance increase along with 40% improved energy efficiency. We will also see 4X improvements in machine learning workloads due to new optimizations in ASIMD procedures and the way dot products are handled. These numbers are based on A75 configurations running at 2.8GHz on 10nm processes, while the A76 is planned by Arm to come in at 3GHz on TSMC-based 7nm products.
The new CPU is naturally still compatible with DynamIQ's common cluster topology, and Arm anticipates that the designs will be paired with the Cortex A55 as the slightly more power-efficient CPUs. The scalability of the DynamIQ IP configuration was reiterated and we were presented with examples of configurations such as 1+7 or 2+6 with Cortex A75 or A76 CPU IP. This presentation slide was one of the few where Arm referred to the A76's surface area, pointing out that the A75 still has a better PPA and may therefore still be a valid design choice for companies depending on their needs. One comparison that was made during the event is that in terms of surface area, three A76s with larger caches would fit the size of a Skylake core - all within 10% of the IPC of an Intel processor, but of course there is node scaling. considerations to take into account.
The exclusive claim is that the Arma aims to outperform the competition in half the space and half the power. Arm has been slightly bashing about what it considers competition here, but generally the answer has been that it considers everyone competition. Considering Intel, AMD or Samsung, it's actually not that hard to imagine Arm beating them in PPA, because historically the company has always had the smallest CPU designs and that translates directly into more efficient microarchitectures.
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Before we get into the more detailed breakdowns of performance and power improvements and what I expect to happen with the products, let's take a look at the micro-architectural improvements to the core and how Arm managed to get so much power while remaining energy efficient.
Starting with a rough overview of the Cortex A76 microarchitectural diagram, we see the larger functional blocks. The A76 doesn't differ much from other Arm processors in this respect, and the differences only come with the details that Arm is willing to reveal. To oversimplify, this is an out-of-order superscalar core with a 4-wide decoding front-end with 8 execution ports in the backend with a total implementation pipeline depth of 13 stages with 11 stage core execution latencies.
In the front-end, Arm has created a new prediction/fetch unit that it calls "predict directed fetch", which means that the branch prediction unit is fed to the instruction fetch unit. This is a departure from previous Arm µarches and allows for higher performance and lower power consumption.
The industry prediction unit is what Arm calls the first in the industry to adopt a hybrid indirect predictor. The predictor is separate from the feed unit and its supporting large structures operate separately from the rest of the machine - presumably this means that it will be easier to clock the gate during operation to save power. The branch predictor is supported by 3-level branch target caches; 16-input nanoBTB, 64-input microBTB and 6000-input main BTB. Arm claimed back in the A73 and A75 branch predictor generations was able to predict almost all branches received, so this new unit in the A76 seems to be a level up in capabilities.
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The branch unit operates at twice the bandwidth of the feeder unit - it operates at 32B/cycle, which means up to 8 32b instructions per cycle. This feeds the fetch queue before the 12 "block" instruction is fetched. The recall unit operates at a speed of 16B/cycle, which means 4 32b instructions. A branch unit operating with double throughput allows to get in front of the supply unit. This serves to hide the branch bubbles in the pipeline in the event of a misprediction and prevent the outrigger and the rest of the core from jamming. It is said that the core can handle up to 8 dishes on the I-side.
I already mentioned at the beginning that the A76 is a 13-core implementation with an 11-core latency. What happens is that the phases can overlap in the latency critical paths. One such cycle occurs between the second cycle of the branch prediction path and the first cycle of the pickup path. So effectively, while there are 4 (2+2) pipeline stages on a branch and load, the core has latencies of up to 3 cycles.
In the decoding and renaming phases, we see a throughput of 4 instructions per cycle. The A73 and A75 were wide in their decoding stages 2 and 3, so the A76 is 33% wider than the previous generation in this aspect. It was interesting to see how the A73 drops in decoding width from the 3-width of the A72, but this was done to optimize power efficiency and pipeline "leanness" to improve utilization of the front-end units. As the A76 is 4-wide, it's also Arms' widest microarchitecture to date – though it's still extremely slim when you put it up against rival µarches from Samsung or Apple.
The calling unit supplies up to 16 32b instructions to the decoding line. The pipeline stages here consist of 2 cycles of aligning and decoding instructions. It looks like Arm has decided to go back to 2-cycle decoding as opposed to the 1-cycle unit found on the A73 and A75. As a reminder, there are still Sophie cores
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